Differential inputs LOAD

Though asynchronous design has been studied for decades, some objective design diicul-ties made synchronous design style more suitable for commercial applications. The promise of no clock skew, the higher degree of modularity, the low power consumption, have generated a resurgence of interest of the scientiic community for asynchronous logic. More than two decades of uncontrasted dominion of synchronous design style, have produced many robust automated design procedures; on the contrary, asynchronous circuits design is challenging because of the problems due to hazards and races, and it is hard to automate the entire design process, especially the synthesis of asynchronous datapaths. In this paper we will describe some recent design methodologies suited for self-timed or fully-asynchronous datapaths.